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4 Jobs - Page 1 of 1 (00:00 seconds)

Senior Semiconductor Layout Engineer

Company

Akaasa Technologies |

Location

San Jose, California, United States ( 0 miles away ) |

Posted date

4 days ago | Onsite

Via CIEPAL_ORGANIC_FEED

Senior Semiconductor Layout Engineer Location: San Jose, CA - Hybrid 3 days per week Position Overview We are seeking an experienced Senior Semiconductor Layout Engineer to develop advanced SRAM and memory IP for next-generation semiconductor technologies. This role focuses on custom IC layout, memory floorplanning, physical verification, and tapeout while working closely with circuit design, physical design, CAD, and process engineering teams. Responsibilities Design and optimize custom layo

Snaprecruit.com - ID: SD-CIE-5833933b6be00044b6b4741e48ef8ed3b5aaa678cf2859ca52896f643b34d920

Job origin: CIEPAL_ORGANIC_FEED

Senior Semiconductor Layout Engineer

Company

Akaasa Technologies |

Location

San Jose, California, United States ( 0 miles away ) |

Posted date

5 days ago | Onsite

Via CIEPAL_ORGANIC_FEED

Senior Semiconductor Layout Engineer Location: San Jose, CA - Hybrid 3 days per week Position Overview We are seeking an experienced Senior Semiconductor Layout Engineer to develop advanced SRAM and memory IP for next-generation semiconductor technologies. This role focuses on custom IC layout, memory floorplanning, physical verification, and tapeout while working closely with circuit design, physical design, CAD, and process engineering teams. Responsibilities Design and optimize custom layo

Snaprecruit.com - ID: SD-CIE-ed9d72274e0c239d31cd4c6874cb68b09382d8e7d1894ebc47f672336ca00a03

Job origin: CIEPAL_ORGANIC_FEED

Senior Semiconductor Layout Engineer

Company

Akaasa Technologies |

Location

San Jose, California, United States ( 0 miles away ) |

Posted date

1 week ago | Onsite

Via CIEPAL_ORGANIC_FEED

Senior Semiconductor Layout Engineer Location: San Jose, CA - Hybrid 3 days per week Position Overview We are seeking an experienced Senior Semiconductor Layout Engineer to develop advanced SRAM and memory IP for next-generation semiconductor technologies. This role focuses on custom IC layout, memory floorplanning, physical verification, and tapeout while working closely with circuit design, physical design, CAD, and process engineering teams. Responsibilities Design and optimize custom layo

Snaprecruit.com - ID: SD-CIE-0724259a62e8047669991585bd67296347a47c60de08fc21d504527b47c851b0

Job origin: CIEPAL_ORGANIC_FEED

Senior Semiconductor Layout Engineer

Company

Akaasa Technologies |

Location

San Jose, California, United States ( 0 miles away ) |

Posted date

1 week ago | Onsite

Via CIEPAL_ORGANIC_FEED

Senior Semiconductor Layout Engineer Location: San Jose, CA - Hybrid 3 days per week Position Overview We are seeking an experienced Senior Semiconductor Layout Engineer to develop advanced SRAM and memory IP for next-generation semiconductor technologies. This role focuses on custom IC layout, memory floorplanning, physical verification, and tapeout while working closely with circuit design, physical design, CAD, and process engineering teams. Responsibilities Design and optimize custom layo

Snaprecruit.com - ID: SD-CIE-3502a9a700da6284ccd31a822c27eb35102fa017edcab840fff4c891d211a563

Job origin: CIEPAL_ORGANIC_FEED

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