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582909-Senior High Speed Mixed-Signal I/O & Analog Layout Engineer

  • Job type Posted on: Jul 06, 2026
  • Experience level Norland Group
  • Employment type San Jose, California
  • Remote status Salary: $228,800 per month
  • Employment type Onsite
  • Salary Full-time

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Job Title :

582909-Senior High Speed Mixed-Signal I/O & Analog Layout Engineer

Job Type :

Full-time

Job Location :

San Jose California United States

Remote :

No

Jobcon Logo Job Description :

Position Title: 582909 - Senior High Speed Mixed-Signal I/O & Analog Layout Engineer Location: San Jose, CA Pay Rate: $100-$110 Contract Duration: 6 months contract Description As a senior high speed mixed-signal layout / analog layout engineer, you will be working with circuit designers located in San Jose, California, USA to accomplish layout tasks. Circuits you will work on include High Speed RX, TX, PLL, CDR, analog reference circuits, and so on. You should have experience doing layout with sub‑micron CMOS technologies. Responsibilities Work with remote circuit designers to determine the chip floorplan and develop strategies to optimize parasitics, reduce area, and improve high‑speed SERDES / analog performance. Estimate schedule and develop a plan to complete tasks within a dedicated time frame. Read design documents provided by the foundry and resolve issues such as latch‑up and DRC violations. Perform custom layout using Virtuoso and obtain LVS / DRC clean. Be familiar with CAD tools, including Virtuoso, Calibre LVS, DRC, SkillCad, and similar. Have experience in chip‑level design such as bump, pad, and ESD strategies. Communicate effectively with circuit designers. Requirements Bachelor’s degree in electrical or computer engineering and 5+ years of professional experience as an IC layout designer, or 8+ years of experience in lieu of a degree. Clear background, drug test, and education check. Authorized to work in the United States for any employer without sponsorship. Preferred Skills Strong high‑speed SERDES / analog layout skills. Experience with advanced nodes in IC layout, including FinFET 14nm, 8nm, 4nm, and 2nm GAA. Experience in IC layouts with frequencies up to 224 Gb/s. Experience in critical IC layouts, such as VCO, clocking circuits, TX, RX, and related functions. Working knowledge of Linux. Proficiency with Cadence Virtuoso, Calibre LVS, DRC, and SkillCad. Excellent communication skills in verbal, email, and documentation. Ability to work independently. Experience leading a small team and tape‑out an analog IC (preferred). EEO/Benefits We encourage minorities, women, protected veterans, and disabled individuals to apply for all positions for which they are qualified. We maintain a drug‑free workplace and perform pre‑employment substance abuse testing and background checks. #J-18808-Ljbffr

Jobcon Logo Position Details

Posted:

Jul 06, 2026

Reference Number:

14660_CF3049350DFF32A9B6674718D262490B

Employment:

Full-time

Salary:

Not Available

City:

San Jose

Job Origin:

APPCAST_CPC

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Position Title: 582909 - Senior High Speed Mixed-Signal I/O & Analog Layout Engineer Location: San Jose, CA Pay Rate: $100-$110 Contract Duration: 6 months contract Description As a senior high speed mixed-signal layout / analog layout engineer, you will be working with circuit designers located in San Jose, California, USA to accomplish layout tasks. Circuits you will work on include High Speed RX, TX, PLL, CDR, analog reference circuits, and so on. You should have experience doing layout with sub‑micron CMOS technologies. Responsibilities Work with remote circuit designers to determine the chip floorplan and develop strategies to optimize parasitics, reduce area, and improve high‑speed SERDES / analog performance. Estimate schedule and develop a plan to complete tasks within a dedicated time frame. Read design documents provided by the foundry and resolve issues such as latch‑up and DRC violations. Perform custom layout using Virtuoso and obtain LVS / DRC clean. Be familiar with CAD tools, including Virtuoso, Calibre LVS, DRC, SkillCad, and similar. Have experience in chip‑level design such as bump, pad, and ESD strategies. Communicate effectively with circuit designers. Requirements Bachelor’s degree in electrical or computer engineering and 5+ years of professional experience as an IC layout designer, or 8+ years of experience in lieu of a degree. Clear background, drug test, and education check. Authorized to work in the United States for any employer without sponsorship. Preferred Skills Strong high‑speed SERDES / analog layout skills. Experience with advanced nodes in IC layout, including FinFET 14nm, 8nm, 4nm, and 2nm GAA. Experience in IC layouts with frequencies up to 224 Gb/s. Experience in critical IC layouts, such as VCO, clocking circuits, TX, RX, and related functions. Working knowledge of Linux. Proficiency with Cadence Virtuoso, Calibre LVS, DRC, and SkillCad. Excellent communication skills in verbal, email, and documentation. Ability to work independently. Experience leading a small team and tape‑out an analog IC (preferred). EEO/Benefits We encourage minorities, women, protected veterans, and disabled individuals to apply for all positions for which they are qualified. We maintain a drug‑free workplace and perform pre‑employment substance abuse testing and background checks. #J-18808-Ljbffr

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