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ASIC Design Engineer X 5

In United States

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ASIC Design Engineer X 5   

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JOB TITLE:

ASIC Design Engineer X 5

JOB TYPE:

JOB SKILLS:

JOB LOCATION:

San Jose, CA United States

JOB DESCRIPTION:

You will be part of the IC design team, creating and bringing to market Client's next generation automotive camera video/vision processors. Located in the Toronto office, you will have the following responsibilities:

  • Architect, design and verify key processing blocks of automotive camera video/vision processors
  • Work closely with the algorithm team to enhance efficiency and performance of next generation image processing elements
  • Design elements of the SOC processing fabric including CPU, high speed interfaces, interconnect fabric, top level clock and reset structures
  • Design of power management structures to achieve the lowest power consumption in multiple operational modes
  • Develop block/system level RTL to meet synthesis/physical, DFT and power goals
  • Develop block architecture & RTL that will meet the functional safety requirements of the chip
  • Collaborate with the physical design team to meet overall physical design targets
  • Work with verification team to develop and review block and chip level verification environments and test plans
  • Work with the systems and software teams on emulation platforms and lead the bring-up of your designed blocks
  • Play a key role in the bring-up of your design elements in the device prototype
  • Provide support to the Product Engineering team to meet all validation, characterization and qualification goals for the product

QUALIFICATIONS

  • BSEE +
  • 8 years of industry experience in digital design
  • A history of working with video/graphics processing
  • Development history with neural network accelerators a plus
  • Experience in RTL design with Verilog/System Verilog
  • Understanding of standard IC design methodology with simulation, synthesis, timing closure and DFT
  • Familiarity with design verification and the ability to independently develop block level test suites
  • Strong programming skills in C and scripting languages such as Python

Position Details

POSTED:

Jan 17, 2023

EMPLOYMENT:

INDUSTRY:

SNAPRECRUIT ID:

S166199049261010218

LOCATION:

United States

CITY:

San Jose, CA

Job Origin:

OORWIN_ORGANIC_FEED

A job sourcing event
In Dallas Fort Worth
Aug 19, 2017 9am-6pm
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<p><span style="font-family: Tahoma,Geneva,sans-serif;">You will be part of the IC design team, creating and bringing to market Client's next generation automotive camera video/vision processors. Located in the Toronto office, you will have the following responsibilities:</span></p> <ul> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Architect, design and verify key processing blocks of automotive camera video/vision processors</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Work closely with the algorithm team to enhance efficiency and performance of next generation image processing elements</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Design elements of the SOC processing fabric including CPU, high speed interfaces, interconnect fabric, top level clock and reset structures</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Design of power management structures to achieve the lowest power consumption in multiple operational modes</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Develop block/system level RTL to meet synthesis/physical, DFT and power goals</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Develop block architecture & RTL that will meet the functional safety requirements of the chip</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Collaborate with the physical design team to meet overall physical design targets</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Work with verification team to develop and review block and chip level verification environments and test plans</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Work with the systems and software teams on emulation platforms and lead the bring-up of your designed blocks</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Play a key role in the bring-up of your design elements in the device prototype</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Provide support to the Product Engineering team to meet all validation, characterization and qualification goals for the product</span></li> </ul> <p><span style="font-family: Tahoma,Geneva,sans-serif;"><strong>QUALIFICATIONS</strong></span></p> <ul> <li><span style="font-family: Tahoma,Geneva,sans-serif;">BSEE +</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">8 years of industry experience in digital design</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">A history of working with video/graphics processing</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Development history with neural network accelerators a plus</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Experience in RTL design with Verilog/System Verilog</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Understanding of standard IC design methodology with simulation, synthesis, timing closure and DFT</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Familiarity with design verification and the ability to independently develop block level test suites</span></li> <li><span style="font-family: Tahoma,Geneva,sans-serif;">Strong programming skills in C and scripting languages such as Python</span></li> </ul>


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