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Sr Advanced Semiconductor Engineer

In Minnesota / United States

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Sr Advanced Semiconductor Engineer   

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JOB TITLE:

Sr Advanced Semiconductor Engineer

JOB TYPE:

JOB SKILLS:

JOB LOCATION:

Plymouth Minnesota / United States

JOB DESCRIPTION:

Mask Layout Designer. Perform Mask Layout Design work using Cadence Virtuosu and perform Physical Verification using Siemens-EDA Calibre. IC mask design layout responsibilities and physical verification ranging from test chips to complete products with work spanning cell-level to chip-level scope.

You Must have:
• US Citizenship is required

Shift Timings:
Time Sheet Type Standard
Time Sheet Frequency Weekly
Hours per Day 8
Hours per Week 40


WE VALUE
• Bachelor’s Degree in Electrical Engineering
• Mask Layout Design experience spanning cell-level layout design to chip-level layout design &verification tasks
• Cadence Process Design Kit (PDK) experience and Virtuoso tool proficiency
• Siemens-EDA (MENTOR) Physical Verification proficiency
• Experience with and working knowledge of CMOS semiconductor technology
• Windows OS and LINUX OS and Microsoft office suite tools proficiency
• Effective and clear communication skills and good ability to work with others
• Work accurately with excellent attention to detail
• Ability to work simultaneously on multiple projects and follow up on responsibilities
• Self-starter who requires minimal oversight

Position Details

POSTED:

May 21, 2022

EMPLOYMENT:

INDUSTRY:

SNAPRECRUIT ID:

S1647961208413657

LOCATION:

Minnesota / United States

CITY:

Plymouth

Job Origin:

Jobsrus_organic_feed

A job sourcing event
In Dallas Fort Worth
Aug 19, 2017 9am-6pm
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Sr Advanced Semiconductor Engineer    Apply

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Mask Layout Designer. Perform Mask Layout Design work using Cadence Virtuosu and perform Physical Verification using Siemens-EDA Calibre. IC mask design layout responsibilities and physical verification ranging from test chips to complete products with work spanning cell-level to chip-level scope.

You Must have:
• US Citizenship is required

Shift Timings:
Time Sheet Type Standard
Time Sheet Frequency Weekly
Hours per Day 8
Hours per Week 40


WE VALUE
• Bachelor’s Degree in Electrical Engineering
• Mask Layout Design experience spanning cell-level layout design to chip-level layout design &verification tasks
• Cadence Process Design Kit (PDK) experience and Virtuoso tool proficiency
• Siemens-EDA (MENTOR) Physical Verification proficiency
• Experience with and working knowledge of CMOS semiconductor technology
• Windows OS and LINUX OS and Microsoft office suite tools proficiency
• Effective and clear communication skills and good ability to work with others
• Work accurately with excellent attention to detail
• Ability to work simultaneously on multiple projects and follow up on responsibilities
• Self-starter who requires minimal oversight


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