Application Specific Integrated Circuit Design Engineer

We’re representing a venture-backed silicon photonics startup building high-performance systems for next-generation AI infrastructure.They’re looking for an ASIC/Digital Design Engineer to help architect and implement high-bandwidth silicon systems that connect compute logic with optically coupled memory and chiplet-based architectures.Experience with:ASIC digital design (RTL in Verilog / SystemVerilog) with tapeout experience in advanced nodes (e.g., 7nm and below preferred)Microarchitecture design of high-performance digital systems (pipelines, interconnects, memory hierarchies)High-speed data movement architectures (NoC, interconnect fabrics, streaming datapaths)High-speed I/O interfaces (PCIe, Ethernet, CXL, SERDES, DDR/HBM, or similar)Memory subsystem design (coherence, buffering, latency optimization, bandwidth scaling)ASIC integration across multiple IP blocks (3rd party IP, internal subsystems, interface bridging)Timing closure, PPA tradeoffs (power, performance, area) in large-scale SoCs or chiplet-based designsSystem-level thinking across compute + interconnect + memory boundariesNice to have:Experience with chiplet architectures or multi-die / heterogeneous integrationBackground in network processors, AI accelerators, or HPC-class SoCsExposure to optical interconnects, silicon photonics, or high-speed SerDes ecosystemsExperience bridging RTL ↔ physical design awareness (timing, floorplanning constraints, congestion-driven architecture decisions)Exposure to AI/ML workloads from a hardware efficiency / data movement perspective (not algorithm development)Remote-friendly (US) with preference for Bay Area proximity.