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Asic Rtl Design Engineer Senior

  • ... Posted on: Feb 11, 2025
  • ... TekWissen LLC
  • ... San Jose, California
  • ... Salary: Not Available
  • ... Full-time

Asic Rtl Design Engineer Senior   

Job Title :

Asic Rtl Design Engineer Senior

Job Type :

Full-time

Job Location :

San Jose California United States

Remote :

No

Jobcon Logo Job Description :

Overview:
TekWissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.
Job Title: ASIC/RTL Design Engineer - Senior
Work Location: San Jose, CA 95124
Duration: 12 Months
Work Type: Contract
Job Type: Onsite
Job Description:
Top skills:
  • RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime).
JOB DUTIES:
  • The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and Client internal IP's.
  • Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes.
  • Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.
EXPERIENCE AND EDUCATION:
  • SoC Design
  • Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification, and supporting synthesis and timing closure.
  • Experience with front end quality checks such as Lint, CDC, RDC. Running, Debugging, Reporting, Driving Cleanup.
  • Working knowledge of ARM cores and other I/O standard interfaces.
  • Roughly 10 years experience, but less is acceptable.
  • Bachelors in electrical engineering or computer engineering is preferred
An ideal candidate would also exhibit:
  • Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership
TekWissen Group is an equal opportunity employer supporting workforce diversity.

Jobcon Logo Position Details

Posted:

Feb 11, 2025

Employment:

Full-time

Salary:

Not Available

Snaprecruit ID:

SD-CIE-1f111f216aaccfd90165b0b14103eb6d5e1d629c41716b54df9c0850c4fb368b

City:

San Jose

Job Origin:

CIEPAL_ORGANIC_FEED

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Overview:
TekWissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.
Job Title: ASIC/RTL Design Engineer - Senior
Work Location: San Jose, CA 95124
Duration: 12 Months
Work Type: Contract
Job Type: Onsite
Job Description:
Top skills:
  • RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime).
JOB DUTIES:
  • The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and Client internal IP's.
  • Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes.
  • Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.
EXPERIENCE AND EDUCATION:
  • SoC Design
  • Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification, and supporting synthesis and timing closure.
  • Experience with front end quality checks such as Lint, CDC, RDC. Running, Debugging, Reporting, Driving Cleanup.
  • Working knowledge of ARM cores and other I/O standard interfaces.
  • Roughly 10 years experience, but less is acceptable.
  • Bachelors in electrical engineering or computer engineering is preferred
An ideal candidate would also exhibit:
  • Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership
TekWissen Group is an equal opportunity employer supporting workforce diversity.

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