Duties: Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction. Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery. Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates. This role expects you to be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks. Your role may include extraction and STA flow development, convergence strategies.

Skills: Degree in Electrical Engineering or Computer Engineering. 8+ years of ASIC STA (Static Timing Analysis) experience. Candidate will be using following tools and must possess below experience of tools: Synopsys Design Compiler/ Synopsys Primetime/ Cadence Tempus Synthesis Tools: Synopsys DC/DCG/FC. Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/Prime Closure, Cadence Tempus. Scripting: TCL, Perl, or Python.

Education: BS/MS in Engineering

Required Skills: ECO,ASIC,CADENCE,BUDGETING,CLOSING,
Additional Skills: SYNOPSYS,QUALITY CHECKS,APPLICATION-SPECIFIC INTEGRATED CIRCUIT,PERL,TCL,PYTHON,SCRIPTING,ELECTRICAL ENGINEERING,

Minimum Degree Required: Bachelor's Degree
Hours Per Day: 8.00
Hours Per Week: 40.00
Languages: English( Speak, Read, Write )
Department: Cost of goods sold : 1100
Job Category: IT