Responsibilities: Responsible for the verification of networking/data center IC designs including creating SystemVerilog-based verification environments and creating and executing test plans for verifications of RTL and gatesim-based designsResponsible for creating ATE testing vectors, as well as C-based diagnostic tests to be run on large SoCs.Requirements:MSEE/Electronics/Computer Science degree and at least 7+years of design verification experienceStrong knowledge and hands-on experience in verification methods, verification tools and environmentsHands-on experience and knowledge of both the block level and top-level verification is requiredExcellent programming skills, including SystemVerilog and scripting languagesKnowledge and experience in UVMKnowledge of networking/switching ICs and concepts is preferredU.S. citizenship or permanent residency