SENIOR STAFF VERIFICATION ENGINEERBRISTOLI have an exciting opportunity for a Senior Staff Verification Engineer to join a global R&D organisation. In this role, you will be responsible for developing SystemVerilog UVM testbench environments for IP-level verification, as well as designing and implementing new UVM verification components.You will ensure that verification environments meet all sign-off criteria, including functional coverage, functional safety requirements, and testbench qualification. A key aspect of the role will be representing the verification perspective in design reviews, working closely with design teams, and contributing to the ongoing development of verification strategy and testbench architecture across the business.Key RequirementsMinimum of 7 years’ experience in hardware verification, ideally at IP level, using SystemVerilog and UVMAdvanced expertise in UVM, SystemVerilog, and SystemVerilog Assertions (SVAs)Experience developing verification platforms and frameworksProven ownership of IP verification, including delivery against defined metrics and sign-off targetsStrong ability to interpret and understand complex design specificationsFor more information and a confidential discussion, please contact Rachel Mason at IC Resources.