Design Verification Engineer

Base Pay Range $60.00/hr - $80.00/hr Essential Skills Must be fluent in the synthesizable constructs of SystemVerilog; should be able to design a basic module without any trouble Must be competent in class-based verification techniques using SystemVerilog; UVM experience is highly preferred, but other frameworks like VMM, OVM, or something custom are still valuable Must be familiar with how to compile and run a simulation, open a design, and debug it using an industry standard simulator like Synopsys’ VCS, Siemens QuestaSim, or Cadence Xcelium Must have a good understanding of the industry landscape; should understand and articulate ASIC and FPGA-relevant concepts Must be able to pick up new techniques quickly and be a strong self‑learner; candidate should be able to design new features thoughtfully after considering all tradeoffs with guidance from senior engineers Nice‑to‑have Skills Write scripts quickly for task automation or result summaries: Python, Bash, Perl, TCL, etc. High speed IO familiarity like Ethernet, PCIe, CXL Design creation with AMD Vivado toolchain; familiarity with various AMD IPs Experience with licensed verification IP (VIP) from Siemens, Cadence, or Synopsys ASIC or FPGA bring‑up after chip tapeout Job Duties Participate in design and functional verification of a block(s) of IP. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block and overall system. Be responsible for developing and improving simulation test environments consisting of directed and constrained‑random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally and work within the existing verification infrastructure. Be familiar with hardware modeling and/or assertion‑based verification methods. In this role you will be part of a PCIe development and productization team. A majority of the verification will target PCIe device testing DMA, CXL, IDE, VIP models, traffic generators/checkers, etc. Experience 3 or more years of verification experience with SystemVerilog for IP or system level verification; a particular focus being deep testbench creation experience and/or agent (AKA BFM) development Familiar with UVM verification methodologies Strong debug skills with simulation tools like QuestaSim, VCS, or Xcelium Strong analytical skills and attention to detail Excellent written and communication skills Familiarity with PCIe and serial protocols is a bonus AMD/Xilinx FPGA and tools experience is a bonus Seniority Level Mid‑Senior level Employment Type Contract Job Function Semiconductor Manufacturing #J-18808-Ljbffr