About MesaQuantum

Mesa Quantum is building the manufacturing backbone of the quantum economy. We specialize

in chip-scale quantum devices—starting with clocks and sensors—that unlock resilient Position,

Navigation, and Timing (PNT) systems. Our team combines world-class expertise in AMO

physics, photonics, microfabrication, and engineering to transform breakthrough science into

scalable and deployable technology. Backed by top-tier deep-tech investors and the U.S.

Department of Defense, Mesa Quantum is rapidly scaling and actively recruiting exceptional

innovators who want to build the future of quantum technology from the ground up.

The Role

We are seeking an experienced Firmware & Algorithms Engineer who can bridge the gap

between embedded systems development and sophisticated software algorithms for PNT

applications. This role requires someone who can both develop robust firmware/HDL for our

chip-scale atomic clocks and sensors, while also implementing advanced algorithms for clock

ensembling, navigation, and threat detection. You'll work at the intersection of embedded

systems, signal processing, and PNT applications—developing everything from low-level

firmware (STM32 microcontrollers and/or FPGA) to high-level algorithms for spoof detection,

jamming mitigation, and Kalman filtering for GPS-denied navigation.

Key Responsibilities

Embedded Firmware & HDL Development

• Design and develop firmware for STM32 microcontrollers and/or FPGA implementations

controlling atomic clocks and quantum sensors

• Implement high-speed signal processing and control loops in FPGA (Verilog/VHDL) for

real-time clock stabilization

• Architect and implement secure over-the-air (OTA) firmware update solutions

• Optimize firmware/HDL for resource-constrained environments (power, memory,

processing, logic resources)

• Develop drivers and integration solutions for sensors and peripherals

• Implement phase-locked loops (PLLs), digital control systems, and frequency synthesis

in FPGA or microcontroller

• Collaborate with hardware teams to ensure optimal firmware-hardware interaction

Algorithm Development & Implementation

• Develop and implement clock ensembling algorithms to combine multiple atomic clock

sources

• Design and implement spoof detection and jamming detection algorithms for GNSS

systems

• Implement Kalman filters and sensor fusion algorithms for GPS-denied navigation

(magnetic navigation, dead reckoning, inertial navigation)

• Develop signal processing algorithms for atomic clock performance optimization

• Create data analysis tools for characterizing device performance (Allan deviation, phase

noise, etc.)

• Implement machine learning models for temperature compensation and aging

compensation of timing devices

System Integration & Architecture

• Define software/firmware architecture for new quantum timing and sensing products

• Design interfaces between embedded firmware and higher-level software systems

• Create APIs and communication protocols for integrating our devices into customer

systems

• Develop testing frameworks and validation tools for both firmware and algorithms

• Participate in design reviews and contribute to architectural decisions across hardware

and software

Technical Leadership

• Take ownership of significant firmware modules and algorithmic subsystems

• Mentor junior engineers on embedded development and algorithm implementation best

practices

• Lead implementation of critical features (OTA updates, sensor fusion, threat detection)

• Make informed trade-offs between performance, accuracy, power consumption, and

development time

• Create and maintain technical documentation for firmware components and algorithms

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering,

Computer Science, Physics, or related technical field

• 5+ years of professional experience developing firmware for embedded systems and/or

HDL for FPGA

• Strong proficiency in C programming for embedded systems and/or Verilog/VHDL for

FPGA development

• Experience with STM32 family of microcontrollers (preferably F4, L4, H7, or WB

series) and/or FPGA platforms (Xilinx, Intel/Altera, Lattice, or Microchip)

• Experience with RTOS (FreeRTOS, ThreadX, or similar) or FPGA state machines and

timing-critical implementations

• Proven experience implementing digital signal processing algorithms (FIR/IIR filters,

FFT, correlation, etc.)

• Practical experience with sensor fusion or state estimation algorithms (Kalman filters,

complementary filters, particle filters)

• Strong mathematical foundation in linear algebra, probability, and statistics

• Experience with communication protocols (UART, SPI, I2C, USB) and at least one

wireless protocol (BLE, WiFi, etc.)

• Proficiency in Python or MATLAB for algorithm prototyping and data analysis

• Experience with debugging tools for embedded systems (logic analyzers, oscilloscopes,

JTAG/SWD)

• Familiarity with version control systems (Git) and code review processes

Required Technical Skills

• Memory management and power optimization in resource-constrained systems

• Real-time signal processing and control loop implementation (firmware or HDL)

• Interrupt handling and real-time constraints / FPGA timing closure and pipelining

• OTA firmware update mechanisms and bootloader concepts

• Hardware abstraction layer (HAL) design

• Digital design fundamentals (for FPGA: state machines, clock domain crossing,

metastability)

• Secure coding practices for embedded systems

• Algorithm validation and performance characterization

• Understanding of digital and analog electronics fundamentals

Highly Desired Qualifications

• Experience with chip-scale atomic clocks, oscillators, or precision timing devices

• Experience with GPS/GNSS systems and PNT applications

• Practical experience implementing clock ensembling or frequency steering

algorithms

• Experience developing spoof detection or anti-jamming algorithms for GNSS

• Machine learning/AI implementation for device compensation (temperature, aging,

drift)

• Experience with FPGA-based phase-locked loops (PLLs) or direct digital synthesis

(DDS)

• Experience implementing high-speed ADC/DAC interfaces and signal conditioning in

FPGA

• Experience with inertial navigation systems (INS) or magnetic navigation

• Background in atomic physics, frequency references, or RF systems

• Experience with timing standards and characterization (IEEE 1588, Allan deviation,

phase noise analysis)

• Knowledge of secure boot concepts and cryptographic implementations

• Experience with continuous integration/continuous deployment (CI/CD) pipelines for

firmware

• Familiarity with IoT communication protocols (MQTT, CoAP)

• Experience with STM32CubeIDE and STM32CubeMX tools

• Published research or patents in PNT, timing systems, or sensor fusion

• Experience with regulatory compliance for timing devices (FCC, CE, MIL-STD)

About You

You're an engineer who thrives at the intersection of embedded systems and advanced

algorithms. You're equally comfortable optimizing interrupt latency in firmware, implementing a

phase-locked loop in an FPGA, and deriving Kalman filter equations on a whiteboard. You have

a deep appreciation for the physics and mathematics underlying precision timing and navigation

systems, but you're also a pragmatic engineer who knows how to ship production-ready code.

You've probably worked on challenging problems in GPS-denied navigation, timing systems, or

sensor fusion—and you're excited to apply that expertise to cutting-edge quantum devices.

You're comfortable working across the full stack from HDL/bare-metal firmware to high-level

algorithms, and you enjoy collaborating with physicists, hardware engineers, and customers to

translate requirements into robust implementations. Most importantly, you're passionate about

building technology that enhances resilience and security in critical infrastructure and defense

applications.

Why Join MesaQuantum

• Work on cutting-edge quantum technology with real-world defense and infrastructure

applications

• Collaborate with world-class scientists and engineers across multiple disciplines

• Significant equity stake in a well-funded, rapidly growing deep-tech startup

• Opportunity to define the architecture and algorithms for next-generation PNT systems

• Direct impact on national security and critical infrastructure resilience

• Competitive salary and comprehensive benefits package

• Hybrid/flexible work environment (location-dependent)