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FPGA Engineer (Design & Verification- UVM Framework)

In Capellen United States

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FPGA Engineer (Design & Verification- UVM Framework)   

JOB TITLE:

FPGA Engineer (Design & Verification- UVM Framework)

JOB TYPE:

Full-time

JOB LOCATION:

San Diego Capellen United States

JOB DESCRIPTION:

Immediate need for a talented FPGA Engineer (Design & Verification- UVM Framework).
This is a Fulltime opportunity with long-term potential and is located in San Diego, CA(Onsite).
Please review the job description below and contact me ASAP if you are interested.

Job ID: 24-04947

Pay Range: $55 - $60/hour.
Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).


Key Responsibilities:

  • Create FPGA requirement specifications from contributing flow down documents.
  • Generate test specifications to track and ensure functional specifications are fully met.
  • Ability to work independently as well as communicate and work well within the FPGA team.
  • Interact with other design groups such as software and controls to facilitate the design integration effort.
  • Apply use of best design practices with a strong bias of what it takes to deliver highly reliable designs.
  • Own quality of all assigned deliverables.
  • Contribute to the specification, design, implementation, and validation of FPGAs within highly reliable electronics for Client s EUV systems.
  • Participate in cross-functional teams and work with multiple engineering groups to outline and create FPGA designs and associated engineering documentation.
  • Design, implement and test new FPGA features while using robust methodologies defined as a part of the design process.
  • Work with advanced technologies including SoC architecture, digital communication (PCIe, 1G+ Ethernet, Ether CAT, etc), photodetectors, signal acquisition, and distributed high precision timestamping.
  • Assist cross-functional teams with the integration of the FPGA designs into the system environment.

Key Requirements and Technology Experience:

  • 15+ years experience in electronic design and verification, with hands-on experience in requirements specification, detailed design, verification plan, design validation and qualification.
  • Deep knowledge of digital design fundamentals, including clock-domain-crossing (CDC).
  • Strong competence of FPGA tooling including synthesis, building, timing analysis and simulation.
  • Experienced with architecting and coding FPGAs using VHDL.
  • Experience with System Verilog and UVM framework proficiency a plus for verification.
  • Hands-on experience with board, module, and system level electronic troubleshooting , including experience with engineering test equipment such as logic analyzers and bus analyzers bash/perl/python scripting a big plus for verification, validation, and process automation.
  • Knowledge of Make file a plus, familiarity with Linux/Unix OS is needed.
  • Knowledge of change management and revision control tools such as SVN or Git will be a plus.
  • Strong communication skills and ownership of solution space, including ability to author technical specifications, and procedures and driving to completion with minimum oversight.
  • Demonstrated ability to work in a process driven environment, with a structured problem-solving approach.
  • BSEE required, MSEE preferred.

Our client is a leading IT industry, and we are currently interviewing to fill this and other similar contract positions.
If you are interested in this position, please apply online for immediate consideration.


Pyramid Consulting, Inc.
provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.

Position Details

POSTED:

EMPLOYMENT:

Full-time

SALARY:

60 per year

SNAPRECRUIT ID:

S-1707239764-6fa48d32ea02541382cf4af80f426bfd

LOCATION:

Capellen United States

CITY:

San Diego

Job Origin:

jpick2

A job sourcing event
In Dallas Fort Worth
Aug 19, 2017 9am-6pm
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FPGA Engineer (Design & Verification- UVM Framework)    Apply

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Immediate need for a talented FPGA Engineer (Design & Verification- UVM Framework). This is a Fulltime opportunity with long-term potential and is located in San Diego, CA(Onsite). Please review the job description below and contact me ASAP if you are interested.
Job ID: 24-04947

Pay Range: $55 - $60/hour. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).

Key Responsibilities:

  • Create FPGA requirement specifications from contributing flow down documents.
  • Generate test specifications to track and ensure functional specifications are fully met.
  • Ability to work independently as well as communicate and work well within the FPGA team.
  • Interact with other design groups such as software and controls to facilitate the design integration effort.
  • Apply use of best design practices with a strong bias of what it takes to deliver highly reliable designs.
  • Own quality of all assigned deliverables.
  • Contribute to the specification, design, implementation, and validation of FPGAs within highly reliable electronics for Client s EUV systems.
  • Participate in cross-functional teams and work with multiple engineering groups to outline and create FPGA designs and associated engineering documentation.
  • Design, implement and test new FPGA features while using robust methodologies defined as a part of the design process.
  • Work with advanced technologies including SoC architecture, digital communication (PCIe, 1G+ Ethernet, Ether CAT, etc), photodetectors, signal acquisition, and distributed high precision timestamping.
  • Assist cross-functional teams with the integration of the FPGA designs into the system environment.

Key Requirements and Technology Experience:

  • 15+ years experience in electronic design and verification, with hands-on experience in requirements specification, detailed design, verification plan, design validation and qualification.
  • Deep knowledge of digital design fundamentals, including clock-domain-crossing (CDC).
  • Strong competence of FPGA tooling including synthesis, building, timing analysis and simulation.
  • Experienced with architecting and coding FPGAs using VHDL.
  • Experience with System Verilog and UVM framework proficiency a plus for verification.
  • Hands-on experience with board, module, and system level electronic troubleshooting , including experience with engineering test equipment such as logic analyzers and bus analyzers bash/perl/python scripting a big plus for verification, validation, and process automation.
  • Knowledge of Make file a plus, familiarity with Linux/Unix OS is needed.
  • Knowledge of change management and revision control tools such as SVN or Git will be a plus.
  • Strong communication skills and ownership of solution space, including ability to author technical specifications, and procedures and driving to completion with minimum oversight.
  • Demonstrated ability to work in a process driven environment, with a structured problem-solving approach.
  • BSEE required, MSEE preferred.

Our client is a leading IT industry, and we are currently interviewing to fill this and other similar contract positions. If you are interested in this position, please apply online for immediate consideration.

Pyramid Consulting, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.


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