IC Design Verification Architect (UVM/SoC, 802.11)

A leading technology firm in San Jose is looking for a skilled engineer to enhance verification methodologies for unit-level MAC layer simulation. This role involves architecting and implementing test infrastructure and requires expertise in UVM verification environments and knowledge of networking protocols. Candidates should possess a BSCS/BSEE or equivalent with significant experience. This position offers an opportunity to work collaboratively in a dynamic environment with competitive compensation. #J-18808-Ljbffr