PCB Layout Engineer

Summary Meta's Reality Labs hardware team is seeking a PCB Layout Engineer to help bring next‑generation virtual and augmented reality devices to life. In this role, you will own the physical design of complex printed circuit boards for wearable devices, headsets, and spatial computing hardware, working at the intersection of signal integrity, power delivery, and miniaturized form factors. You will collaborate closely with electrical engineers, mechanical engineers, and manufacturing partners to translate schematic designs into manufacturable, high‑performance PCB layouts that meet the demanding constraints of consumer wearable products. PCB Layout Engineer Responsibilities Own end‑to‑end PCB layout for complex, high‑density designs used in VR headsets, AR glasses, and wearable computing devices Perform high‑speed digital layout including DDR, PCIe, USB, and MIPI interfaces with attention to controlled impedance, length matching, and crosstalk mitigation Develop and enforce layout design rules for RF, analog, mixed‑signal, and power domains within tightly constrained wearable form factors Collaborate with electrical engineers to review schematics and provide layout‑driven feedback on component placement, power distribution network design, and signal routing strategies Partner with mechanical engineers to resolve physical constraints including board outline, connector placement, thermal management, and stack‑up definition Drive design‑for‑manufacturability reviews with contract manufacturers and PCB fabricators to ensure layouts meet yield and reliability targets Conduct pre‑ and post‑layout signal integrity and power integrity analysis in collaboration with simulation engineers, iterating on routing to meet timing and noise margins Maintain and improve PCB design standards, layer stack‑up libraries, and footprint libraries to support scalable development across multiple hardware programs Support hardware bring‑up and debug by providing layout documentation, net tracing support, and design revision analysis for prototype and production boards Minimum Qualifications 6+ years of experience in PCB layout design for high‑speed digital, analog, or mixed‑signal consumer electronics products Experience with high‑density interconnect (HDI) and rigid‑flex PCB design for space‑constrained or wearable hardware Experience performing layout for high‑speed interfaces such as DDR, PCIe, USB 3.x, or MIPI CSI/DSI with controlled impedance and differential pair routing Experience collaborating with electrical and mechanical engineering teams through schematic review, design‑for‑manufacturability, and hardware bring‑up phases Proficiency with industry‑standard PCB layout tools such as Cadence Allegro, Mentor Xpedition, or equivalent Preferred Qualifications Experience with rigid‑flex stack‑up design and flex circuit routing for wearable or compact form‑factor hardware Knowledge of RF layout techniques including antenna keep‑out zones, shielding strategies, and coexistence considerations for wireless wearable products Experience designing PCBs for wearable devices, AR/VR headsets, or other miniaturized consumer electronics with strict size, weight, and power constraints Familiarity with signal integrity and power integrity simulation tools (e.g., HyperLynx, Sigrity, or equivalent) and ability to interpret simulation results to guide layout decisions Public Compensation $144,000/year to $204,000/year + bonus + equity + benefits Industry Internet Equal Opportunity Meta is proud to be an Equal Employment Opportunity and Affimative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E‑Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at . #J-18808-Ljbffr