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Principal Digital Verification Engineer

  • Principal Digital Verification Engineer job type Posted on: Nov 02, 2026
  • Principal Digital Verification Engineer experience level European Tech Recruit
  • Principal Digital Verification Engineer employment type Rochester, New York
  • Principal Digital Verification Engineer employment type Onsite
  • Principal Digital Verification Engineer salary Full-time

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Job Title :

Principal Digital Verification Engineer

Job Type :

Full-Time

Job Location :

Rochester New York United States

Remote :

No

Jobcon Logo Job Description :

Principal Digital Verification Engineer - Rochester, NYWe are seeking an experienced Principal Digital Verification Engineer to help develop and verify advanced digital technologies used in high-performance optical communications and networking systems.You will help define verification strategies, drive coverage closure and ensure that complex digital designs meet their functional and performance requirements. The position offers the opportunity to influence verification methodology, contribute to architectural decisions and provide technical leadership across multidisciplinary engineering teams.What you will be doingAnalyse system architecture, digital design specifications and functional requirements in collaboration with systems engineers and architects.Develop and execute verification strategies for complex digital subsystems using simulation, formal verification and functional coverage methodologies.Create, review and optimise SystemVerilog/UVM verification environments, test scenarios and regression strategies.Develop comprehensive functional coverage plans and verification plans to ensure requirements are thoroughly tested.Apply assertions and other verification techniques to identify design issues and improve verification effectiveness.What we are looking forA Bachelor's degree or higher in Electrical Engineering, Computer Engineering, Computer Science or a related technical discipline.At least 12 years of relevant experience in digital design verification.Extensive hands-on experience with SystemVerilog, UVM and SystemVerilog Assertions (SVA).Experience working with industry-standard digital verification simulators.A proven track record of defining and implementing comprehensive verification strategies for complex digital designs.Strong understanding of functional verification, functional coverage, test planning and coverage closure.Experience debugging complex technical issues using a systematic and analytical approach.The ability to work independently, take ownership of technical deliverables and collaborate effectively across engineering teams.Strong written and verbal communication skills in English.Desirable experienceFormal verification methodologies and tools.Digital signal processing (DSP).Forward Error Correction (FEC) or error-correction algorithms.High-speed communications, optical networking or telecommunications silicon.ASIC verification leadership, technical project ownership or mentoring other engineers.Jira or similar tools for issue tracking and Git for version control.Python, Make, Bash or other scripting and automation technologies.

Jobcon Logo Position Details

Posted:

Nov 02, 2026

Reference Number:

10440_4484441434

Employment:

Full-time

City:

Rochester

Job Origin:

APPCAST_CPC

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Principal Digital Verification Engineer - Rochester, NYWe are seeking an experienced Principal Digital Verification Engineer to help develop and verify advanced digital technologies used in high-performance optical communications and networking systems.You will help define verification strategies, drive coverage closure and ensure that complex digital designs meet their functional and performance requirements. The position offers the opportunity to influence verification methodology, contribute to architectural decisions and provide technical leadership across multidisciplinary engineering teams.What you will be doingAnalyse system architecture, digital design specifications and functional requirements in collaboration with systems engineers and architects.Develop and execute verification strategies for complex digital subsystems using simulation, formal verification and functional coverage methodologies.Create, review and optimise SystemVerilog/UVM verification environments, test scenarios and regression strategies.Develop comprehensive functional coverage plans and verification plans to ensure requirements are thoroughly tested.Apply assertions and other verification techniques to identify design issues and improve verification effectiveness.What we are looking forA Bachelor's degree or higher in Electrical Engineering, Computer Engineering, Computer Science or a related technical discipline.At least 12 years of relevant experience in digital design verification.Extensive hands-on experience with SystemVerilog, UVM and SystemVerilog Assertions (SVA).Experience working with industry-standard digital verification simulators.A proven track record of defining and implementing comprehensive verification strategies for complex digital designs.Strong understanding of functional verification, functional coverage, test planning and coverage closure.Experience debugging complex technical issues using a systematic and analytical approach.The ability to work independently, take ownership of technical deliverables and collaborate effectively across engineering teams.Strong written and verbal communication skills in English.Desirable experienceFormal verification methodologies and tools.Digital signal processing (DSP).Forward Error Correction (FEC) or error-correction algorithms.High-speed communications, optical networking or telecommunications silicon.ASIC verification leadership, technical project ownership or mentoring other engineers.Jira or similar tools for issue tracking and Git for version control.Python, Make, Bash or other scripting and automation technologies.

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