Principal Signal Integrity Power Integrity Engineer

Title: Principal Signal Integrity / Power Integrity Engineer

Location: San Jose, CA (ONSITE)

Duration: 6-12 month contract (CTH - no fee)

Job Description:

• As Principal Engineer, System HW Design - SI/PI, you will be part of the Systems Hardware Engineering Team that designs, builds, brings-up, and productizes PCB boards for Client.

• This showcases Client's MLSoC Machine Learning SoC across bring-up and debug, characterization, customer samples, and eventual production. In this role, you will define and drive SI/PI strategy across our entire MLSoC product line - spanning System-on-Module designs, PCIe add-in cards, chip-down BGA reference designs, and full development platforms. This is a significant technical contributor role that will define how signal and power integrity (SI/PI) is implemented across the hardware organization. Working with internal teams and external vendors, the role will guide PCB design, simulation, and lab validation to ensure reliable high-speed signaling and power delivery across our hardware platforms.

Role & responsibilities:

• Define, document (including simulation reports and design decisions),own SI/PI architecture, design guidelines, review processes, and sign-off criteria across the full Client product portfolio (SoM, PCIe HHHL card, chip-down BGA design, DevKit carrier, and future platforms).
• Serve as the technical specialist on high-speed interface margin closure: PCIe Gen5 (root complex, up to 32 GT/s/lane), MIPI CSI/DSI (C-PHY/D-PHY), USB 3.x/Type-C, 10 Gigabit Ethernet SerDes, and LPDDR memory channels
• Drive stack-up, impedance, and channel budget decisions across concurrent board programs, resolving trade-offs between cost, manufacturability, and signal margin at the product-line level
• Own power delivery network (PDN) architecture for high-transient-current AI accelerator silicon, setting design targets and review standards used across all boards
• Set the long-term connector/interconnect strategy across product generations (board-to-board, M.2 NVMe, PCIe edge-card interfaces)
• Define lab validation standards and own escalation-level debug for the hardest SI/PI bring-up issues across programs
• Own the SI/PI simulation tool strategy and flow (Ansys HFSS/SIwave, Cadence Sigrity/Clarity, Keysight ADS, or equivalent) - evaluate and select tools, and build reusable methodology assets for the team
• Own or support compliance testing (PCIe-SIG, USB-IF, MIPI Alliance) for interfaces on production and pre-production boards
• Engage with component/module vendors and standards bodies as needed to stay ahead of emerging high-speed interface requirements

Minimum Requirements:

• Bachelor's in Electrical Engineering or a related field. Master's degree preferred with 15 years of industry experience in signal integrity and power integrity engineering for high-speed digital systems, including experience leading SI/PI strategy across multiple concurrent programs
• Deep, demonstrated expertise with PCIe Gen4/Gen5, DDR4/DDR5/LPDDR, USB 3.x, and MIPI D-PHY/C-PHY signaling, including having driven margin closure on production designs
• Proven track record owning PDN architecture for high-power SoCs/ASICs (AI accelerators, GPUs, or comparable compute silicon) at a product-line level
• Expert-level proficiency with SI/PI EDA tools: Ansys HFSS/SIwave, Cadence Sigrity/Clarity, Keysight ADS, or similar, including tool selection and methodology development
• Extensive hands-on lab validation experience - VNA, TDR, high-bandwidth oscilloscopes - and experience owning escalation-level debug
• Expertise in PCB stack-up design, transmission line theory, S-parameters, and channel modeling.
• Strong working knowledge of industry compliance standards (PCIe-SIG, USB-IF, MIPI Alliance)
• Demonstrated ability to set technical direction and standards across a hardware organization, and to mentor senior/staff-level engineers
• Good cross-functional leadership skills - comfortable driving alignment across ASIC, package, hardware, layout, and firmware teams at a strategic level
• Knowledge of ASIC characterization, PCB manufacturing, assembly, test, quality & reliability is a plus.

The Principal Engineer, System HW Design - SI/PI at in an organizational technical lead responsible for defining and owning the end-to-end signal integrity and power integrity (SI/PI) strategy across the entire MLSoC product line-spanning System-on-Modules (SoMs), PCIe add-in cards, chip-down BGA designs, and development carrier boards.

In this role, the individual will drive margin closure for ultra-high-speed interfaces (PCIe Gen5, MIPI C-PHY/D-PHY, LPDDR, USB 3.x, and 10GbE SerDes), architect robust power delivery networks (PDN) to handle high-transient AI accelerator loads, optimize PCB stack-ups and channel budgets, and select enterprise-level simulation tooling and workflows. Beyond modeling and simulation, they will lead hands-on high-bandwidth lab validation, compliance testing, and escalation-level hardware bring-up debug while establishing company-wide SI/PI sign-off criteria and mentoring engineering teams.