TekWissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.

Job Type: Onsite

• Responsible for RTL design using Verilog HDL for implementation and debug.
• Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions.
• Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation.

• Perform RTL design of digital components in Verilog/systemverilog.
• Analyze/fix Lint and CDC errors of the components.
• Guarantee quality/timely deliverables meeting project's schedule.
• Help to improve/automate design process.

• 7-15 years' relevant experience
• Experience with RTL design integration tasks
• Multi-clock domain designs.
• Design constraints for synthesis and static timing analysis.
• Knowledge of front-end RTL design tools and methodologies.
• Knowledge of scripting languages like Perl, tcl or cshell

• SOC Design integration tasks such as (RTL integration, Simulation, Debug, Synthesis, STA Constraints, scripting/automation)
• Creating technical documentations such as Microarchitecture documentation, Integration guides

• High speed serial interfaces (such as PCIe, CXL etc.)
• Experience with of AXI protocol
• UPF

• Bachelor's (required) or Master's in Computer Engineering