Senior AI SoC Verification Engineer (SystemVerilog/UVM)

Actalent is seeking a Senior Design Verification Engineer in Santa Clara, CA to verify next-generation AI SoC platforms. You will collaborate with architects, RTL designers, and software teams to ensure correctness, performance, reliability, and safety of complex hardware systems. You will develop verification environments, testbenches, and coverage models, driving functional coverage while mentoring junior engineers and improving methodologies. #J-18808-Ljbffr