We're partnered with a global semiconductor innovator developing high-performance timing and precision technologies used in advanced electronics across communications, data infrastructure, automotive, and industrial markets.They are now looking for a Senior Verification Engineer to join their team in Delft.**Please note this role is fully onsite.**ResponsibilitiesDevelop SystemVerilog Real-Number Models (SV-RNM) for analog and mixed-signal circuitsCreate verification plans based on chip-level and block-level specificationsBuild and maintain UVM verification environments (scoreboards, monitors, sequencers, etc.)Lead digital top-level verification using SystemVerilogDefine and implement SystemVerilog Assertions (SVA)Develop functional coverage models and covergroupsRun simulations, analyze results, and debug issuesReview verification outcomes to support tape-out sign-offCollaborate closely with design, test, and verification stakeholders to ensure strong teamwork and effective knowledge sharingMinimum RequirementsMS (or BS) in Electrical/Computer Engineering or a related field with 5+ (or 8+) years of semiconductor verification experienceStrong written and verbal English communication skillsProficiency in SystemVerilog and object-oriented programming conceptsHands-on experience with UVM-based verification methodologiesStrong experience developing SystemVerilog Assertions (SVA)Proficiency with scripting languages such as Python or PerlAbility to read analog schematics and practical experience with Cadence VirtuosoWorking knowledge of digital design using VerilogExperience collaborating with globally distributed mixed-signal, digital, and analog engineering teamsSelf-driven, with the ability to work independently and solve complex technical challengesDesired QualificationsExperience modeling analog functional behavior using SystemVerilog RNM, wreal (Verilog-AMS), or similar approachesFamiliarity with UVM-AMS methodologiesStrong background in Formal Property Verification (FPV)Object-oriented programming experience in C++Experience in analog mixed-signal verificationSolid understanding of analog design principlesKnowledge of synthesizable digital designExperience verifying datapath designs, including filter implementationsProven ability to thrive in fast-paced, collaborative engineering environmentsExcellent written and verbal communication skillsBy applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice