Senior FPGA Engineer

Senior FPGA Engineer - Radar Systems

Location: Seattle, WA

Work arrangement: On-site

Experience: 8+ years (Flexible)

An innovative space technology company in Seattle is seeking a Senior FPGA Engineer to lead RTL design and FPGA development for advanced radar systems. You will play a key role in translating radar algorithms into reliable, mission-critical firmware while working across hardware, software, mechanical, and signal-processing disciplines.

This position is ideal for an experienced engineer who can independently own complex projects, make sound architectural decisions, and deliver high-quality solutions on schedule in a fast-moving startup environment.

The Role

\n
• Partner with a multidisciplinary engineering team to define and refine firmware requirements.
\n
• Architect, design, and implement embedded firmware for a radar sensor payload.
\n
• Develop control and signal-processing functions in Verilog or VHDL.
\n
• Evaluate implementation complexity, maintainability, and FPGA resource requirements, including logic cells, embedded memory, and DSP slices.
\n
• Produce technical trade studies to support architecture and implementation decisions.
\n
• Integrate RTL designs onto FPGA and SoC platforms through synthesis, place and route, timing analysis, and timing closure.
\n
• Lead bring-up, verification, and validation of FPGA designs on prototype and flight hardware.
\n
• Collaborate with radar algorithm, electrical, software, and mechanical engineers to build dependable embedded systems.
\n
• Support the recruitment, interviewing, and hiring of additional engineering team members.
\n

Required Skills And Experience

\n
• BS or MS in Electrical Engineering, Computer Engineering, or a related discipline.
\n
• At least 8 years of embedded firmware development experience, ideally involving radar or other mission-critical systems.
\n
• Strong RTL design experience using Verilog and/or VHDL, including work on satellite or aerospace applications.
\n
• Hands-on experience bringing up and verifying RTL-based designs on target hardware.
\n
• Experience integrating FPGA or SoC designs, including synthesis, place and route, and timing analysis.
\n
• Familiarity with low-speed interfaces such as I2C, SPI, UART, and RS-422.
\n
• Ability to read and interpret electrical schematics.
\n
• Experience with Git, CI pipelines, code reviews, and version-control workflows.
\n
• Ability to work independently, stay organized, and deliver in a lean, rapidly evolving environment.
\n

Preferred Experience

Experience in any of the following areas would be valuable:

\n
• Distributed digital system design and implementation.
\n
• Clock-domain crossing and timing closure.
\n
• AMD UltraScale+ platforms.
\n
• High-speed ADC and DAC interfaces, including JESD204.
\n
• Signal-processing algorithm implementation in RTL.
\n
• Embedded architectures involving multiple FPGAs and peripheral interfaces such as SPI, UART, GPIO, I2C, and Ethernet.
\n
• Efficient, low-latency data movement between FPGAs, processors, storage devices, and networking interfaces.
\n
• Ethernet and TCP/IP networking stacks.
\n
• Radar, satellite, aerospace, or other high-reliability applications.
\n
• Eligibility and ability to obtain and maintain a Top Secret security clearance.
\n

You do not need to meet every listed qualification. Engineers with strong FPGA fundamentals, relevant mission-critical development experience, and the ability to learn quickly are encouraged to apply.