Senior Principal Fpga Engineer Onsite Cedar

Job Title: Senior / Principal FPGA Engineer
Location: Cedar Rapids, IA 100% Onsite
Job Type: Contract
Shift: 1st Shift, Monday Friday
Pay Rate: $55 $68/hr. on W2
Citizenship: U.S. Citizen required
Clearance: Must be able to obtain a Secret clearance; active clearance is not required to apply.

We are seeking experienced Senior / Principal FPGA Engineers to support advanced defense electronics and microelectronics programs. The role focuses on FPGA/ASIC design, signal processing, verification, integration, and optimization of high-performance digital systems.

• Design, develop, implement, verify, and integrate FPGA/ASIC solutions.

• Develop and implement signal-processing algorithms for FPGA-based systems.

• Use VHDL/Verilog, MATLAB, and Simulink for design, modeling, and simulation.

• Perform digital circuit architecture, timing analysis, resource optimization, and timing closure.

• Integrate FPGA designs with target hardware and support system-level testing and lab validation.

• Support peer reviews, certification activities, requirements analysis, and engineering documentation.

• Troubleshoot FPGA/ASIC systems and support continuous improvement of development processes.

• Collaborate with cross-functional engineering teams and provide technical leadership on advanced projects.

• Bachelor's degree in STEM or related field.

• Senior: 5+ years relevant experience; Principal: 8+ years relevant experience.

• Strong professional experience in FPGA development, ASIC front-end design, or related areas.

• Proficiency with VHDL and/or Verilog.

• Experience with FPGA platforms and tools such as AMD/Xilinx, Altera, Microchip, Vivado, Quartus, or Libero.

• Strong understanding of digital circuit architecture, timing analysis, resource tradeoffs, and timing closure.

• FPGA/ASIC debugging and troubleshooting experience.

• Experience with Git, Subversion, or similar version-control tools.

• Ability to work onsite in Cedar Rapids, IA.

• Signal processing / DSP experience including filtering, modulation, demodulation, and spectral analysis.

• MATLAB / Simulink and HDL Coder experience.

• SystemVerilog, constrained-random verification, and functional coverage.

• High-speed interfaces such as DDR, PCIe, and Ethernet.

• FPGA/ASIC laboratory validation and advanced test equipment.

• Unix/Linux, scripting, C/C++, or Perl.

• Experience providing technical leadership and mentoring engineering teams.

#FPGAEngineer #SeniorFPGAEngineer #PrincipalFPGAEngineer #FPGA #FPGADevelopment #FPGAEngineering #ASIC #ASICDesign #ASICEngineer #VHDL #Verilog #SystemVerilog #DigitalDesign #DigitalEngineering #SignalProcessing #DSP #MATLAB #Simulink #HDLCoder #FPGAValidation #FPGAIntegration #FPV #TimingAnalysis #TimingClosure #DigitalCircuitDesign #Vivado #Xilinx #AMDXilinx #Altera #IntelFPGA #Quartus #Microchip #Libero #HighSpeedDigital #DDR #PCIe #Ethernet #FPGAverification #ASICVerification #HardwareDesign #HardwareTesting #LabValidation #Git #Linux #Unix #Cpp #CProgramming #AerospaceJobs #DefenseJobs #DefenseEngineering #AerospaceEngineering #Microelectronics #Avionics #EngineeringJobs #CedarRapidsJobs #CedarRapidsIA #IowaJobs #OnsiteJobs #ContractJobs #W2Jobs #USCitizen #USCitizensOnly #Hiring #NowHiring