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Senior Rtl Sta Engineer

  • Senior Rtl Sta Engineer job type Posted on: Nov 10, 2026
  • Senior Rtl Sta Engineer experience level AIT Global inc
  • Senior Rtl Sta Engineer employment type San Jose, California
  • Senior Rtl Sta Engineer employment type Onsite
  • Senior Rtl Sta Engineer salary Full-time
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Job Title :

Senior Rtl Sta Engineer

Job Type :

Full-Time

Job Location :

San Jose California United States

Remote :

No

Jobcon Logo Job Description :

Job Title: Senior RTL / STA Engineer
Location: San Jose, CA
Role Overview:
Cisco's ASIC Engineering group is seeking a senior RTL / Static Timing Analysis (STA) contractor to support timing constraint development and verification, RTL design, and timing closure across ASIC design flows. The preferred work location is Cisco's San Jose campus. Candidates with at least 8 years of relevant experience are preferred; candidates with somewhat less experience may be considered when they bring exceptional, directly relevant experience.
Key Responsibilities:
  • Develop, review, debug, and verify timing constraints for ASIC designs.
  • Contribute to RTL design and collaborate with design, verification, synthesis, and DFT teams to resolve timing and implementation issues.
  • Analyze timing behavior and support timing closure across functional and test operating modes, including DFT modes where applicable.
  • Debug timing constraints and reports using industry-standard STA and synthesis tools.
  • Use scripting and automation to improve constraint checks, analysis, and engineering workflows.
Minimum Qualifications:
  • Bachelor's degree and 8 years of related experience, or Master's degree and 6 years of related experience, or PhD and 3 years of related experience.
  • Prior hands-on experience developing and verifying timing constraints.
  • Prior hands-on experience with RTL design.
  • Programming experience with at least two of the following: Perl, Tcl, Python, or Makefile.
Preferred Qualifications:
  • Master's degree with 15+ years of experience.
  • Experience debugging and analyzing PCIe timing constraints and TSMC memory timing constraints.
  • Experience with RTL design, CDC/RDC, and Conformal verification.
  • Experience debugging and analyzing timing constraints and closing timing for DFT modes, including scan shift/capture and BIST.
  • Experience debugging SDC and using Synopsys TCM and PrimeTime STA tools.
  • Experience with Synopsys Fusion Compiler and Design Compiler synthesis tools.
  • Experience with Tessent, including DFT insertion in RTL.

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Jobcon Logo Position Details

Posted:

Nov 10, 2026

Reference Number:

4597-8252

Employment:

Full-time

City:

San Jose

Job Origin:

CIEPAL_ORGANIC_FEED

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Job Title: Senior RTL / STA Engineer
Location: San Jose, CA
Role Overview:
Cisco's ASIC Engineering group is seeking a senior RTL / Static Timing Analysis (STA) contractor to support timing constraint development and verification, RTL design, and timing closure across ASIC design flows. The preferred work location is Cisco's San Jose campus. Candidates with at least 8 years of relevant experience are preferred; candidates with somewhat less experience may be considered when they bring exceptional, directly relevant experience.
Key Responsibilities:
  • Develop, review, debug, and verify timing constraints for ASIC designs.
  • Contribute to RTL design and collaborate with design, verification, synthesis, and DFT teams to resolve timing and implementation issues.
  • Analyze timing behavior and support timing closure across functional and test operating modes, including DFT modes where applicable.
  • Debug timing constraints and reports using industry-standard STA and synthesis tools.
  • Use scripting and automation to improve constraint checks, analysis, and engineering workflows.
Minimum Qualifications:
  • Bachelor's degree and 8 years of related experience, or Master's degree and 6 years of related experience, or PhD and 3 years of related experience.
  • Prior hands-on experience developing and verifying timing constraints.
  • Prior hands-on experience with RTL design.
  • Programming experience with at least two of the following: Perl, Tcl, Python, or Makefile.
Preferred Qualifications:
  • Master's degree with 15+ years of experience.
  • Experience debugging and analyzing PCIe timing constraints and TSMC memory timing constraints.
  • Experience with RTL design, CDC/RDC, and Conformal verification.
  • Experience debugging and analyzing timing constraints and closing timing for DFT modes, including scan shift/capture and BIST.
  • Experience debugging SDC and using Synopsys TCM and PrimeTime STA tools.
  • Experience with Synopsys Fusion Compiler and Design Compiler synthesis tools.
  • Experience with Tessent, including DFT insertion in RTL.

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