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Slt Test Engineer Software Hardware

  • ... Posted on: Dec 13, 2024
  • ... Goldenpick Technologies
  • ... Mountain View, California
  • ... Salary: Not Available
  • ... CTC

Slt Test Engineer Software Hardware   

Job Title :

Slt Test Engineer Software Hardware

Job Type :

CTC

Job Location :

Mountain View California United States

Remote :

No

Jobcon Logo Job Description :

SLT Test Engineer (Software/Hardware)

Responsibilities & opportunities in this role:

  • Own design and validation of System Level Test from software perspective.
  • Write code to help communicate SLT handler to test controller and to peripherals like temperature control units
  • Write test methods, scripts and code to create a test Flow encompassing all the key system level tests provided by the systems validation team
  • Automate and integrate SLT tests to create a master Test flow for the SLT testing on the handler
  • Develop custom tests on the system level to create the most effective screen tests for SLT
  • Define HVM (High Volume Manufacturing) test requirements, collaborate closely with System architecture, chip design, and System validation teams to help create production ready SLT flows
  • Collaborate with chip design and system validation teams to develop a test plan for System to Tester correlation for optimizing power and performance
  • Drive SLT handler selection for a customized SLT solution
  • Drive SLT handler enablement by working closely with multiple vendors
  • Define and drive PCB designs for the SLT solution
  • Define and drive SLT hardware solutions for sockets, Temperature control units etc.
  • Drive the selection of system test requirements for NPI, HVM, platform to platform correlation, and RMAs
  • Work with chip test (ATE) and System Validation teams to decide how to improve the overall manufacturing test coverage
  • Establish network connectivity by understanding the network topology
  • Datalog manipulation to fit industry standards
  • Provide production sustaining support at OSAT for DPPM reduction, yield analysis, RMA debug, and test time reduction
  • Support Silicon Qual activities (HTOL/Burn In) from a system level

Ideal candidates have/are:

  • MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering
  • 10+ years experience in Systems Level Test, Systems validation, and/or bench testing.
  • Experience in day zero bring up of new silicon at the system level
  • Experience in driving SLT testing in HVM
  • Experience with testing and characterization of high power Ips like TPUs, CPUs, GPUs in mission mode.
  • Experience with testing and characterization of High Speed SerDes based IPs (PCIe, Ethernet SerDes etc.)
  • Knowledge of network topology and experience in network connectivity (HW and SW)
  • Proficient in C#, C/C++, PERL, Python, .NET framework
  • Experience in Security provisioning and knowledge of Fuse programming implementation

Jobcon Logo Position Details

Posted:

Dec 13, 2024

Employment:

CTC

Salary:

Not Available

Snaprecruit ID:

SD-CIE-5e81a2a97c4e03ad66d2734cb1bf250a4629a8f02192f19761fb4e5399962519

City:

Mountain View

Job Origin:

CIEPAL_ORGANIC_FEED

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SLT Test Engineer (Software/Hardware)

Responsibilities & opportunities in this role:

  • Own design and validation of System Level Test from software perspective.
  • Write code to help communicate SLT handler to test controller and to peripherals like temperature control units
  • Write test methods, scripts and code to create a test Flow encompassing all the key system level tests provided by the systems validation team
  • Automate and integrate SLT tests to create a master Test flow for the SLT testing on the handler
  • Develop custom tests on the system level to create the most effective screen tests for SLT
  • Define HVM (High Volume Manufacturing) test requirements, collaborate closely with System architecture, chip design, and System validation teams to help create production ready SLT flows
  • Collaborate with chip design and system validation teams to develop a test plan for System to Tester correlation for optimizing power and performance
  • Drive SLT handler selection for a customized SLT solution
  • Drive SLT handler enablement by working closely with multiple vendors
  • Define and drive PCB designs for the SLT solution
  • Define and drive SLT hardware solutions for sockets, Temperature control units etc.
  • Drive the selection of system test requirements for NPI, HVM, platform to platform correlation, and RMAs
  • Work with chip test (ATE) and System Validation teams to decide how to improve the overall manufacturing test coverage
  • Establish network connectivity by understanding the network topology
  • Datalog manipulation to fit industry standards
  • Provide production sustaining support at OSAT for DPPM reduction, yield analysis, RMA debug, and test time reduction
  • Support Silicon Qual activities (HTOL/Burn In) from a system level

Ideal candidates have/are:

  • MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering
  • 10+ years experience in Systems Level Test, Systems validation, and/or bench testing.
  • Experience in day zero bring up of new silicon at the system level
  • Experience in driving SLT testing in HVM
  • Experience with testing and characterization of high power Ips like TPUs, CPUs, GPUs in mission mode.
  • Experience with testing and characterization of High Speed SerDes based IPs (PCIe, Ethernet SerDes etc.)
  • Knowledge of network topology and experience in network connectivity (HW and SW)
  • Proficient in C#, C/C++, PERL, Python, .NET framework
  • Experience in Security provisioning and knowledge of Fuse programming implementation

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