Location: Mountain View, CA (Preferred)/ Can be considered remote.Job Description:What candidate will Be Doing:At-least 10+ years of experience in System Verilog HVL and C++/CAt-least 10+ year of experience in UVM.Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.Proficient in SVTB/UVM, C