Custom Layout Engineer

MediaTek is a leading global fabless semiconductor company powering more than 2 billion devices a year. Our cutting‑edge system‑on‑chip solutions enable some of the world’s most popular smartphones, smart TVs, connectivity products, IoT devices, and more. We combine deep engineering expertise with a collaborative, fast‑paced work environment where innovation, curiosity, and teamwork drive everything we do. Our analog/mixed‑signal design team is seeking a talented Custom Layout Engineer to join our Austin, TX or San Diego, CA office. The team develops high‑performance mixed‑signal and custom digital IP that is central to MediaTek’s next‑generation products. You will collaborate closely with world‑class circuit designers and cross‑functional partners to deliver robust, high‑quality silicon in advanced technology nodes. Key Responsibilities Develop and implement custom layout for analog and mixed‑signal blocks, including ADC, DAC, op‑amp, bandgap reference, flip‑flops/latches, and custom digital circuits. Perform block‑level layout design and top‑level integration in advanced process technologies (FinFET nodes from ~16 nm to 2 nm). Execute and close full verification flows, including DRC, LVS, DFM, and related checks, to achieve sign‑off quality. Analyze and resolve physical design issues, including layout‑dependent effects, matching, noise coupling, and complex design rule constraints. Interpret and apply foundry design rules and design reference manuals to ensure compliance at both block and chip‑top levels. Update, modify, and optimize existing layouts from prior tape‑outs to meet new specifications, performance targets, or technology revisions. Collaborate closely with circuit design engineers, physical design, and other cross‑functional teams throughout the design and tape‑out lifecycle. Main Requirements and Qualifications 5+ years of hands‑on experience working with deep‑submicron FinFET technologies (approximately 16 nm to 2 nm). Strong experience with at least one custom layout tool, such as Cadence Virtuoso or Synopsys Custom Compiler. Solid understanding and experience in validating LVS/DRC/ERC/ANT/ESD/LPE. Proven ability to read, interpret, and apply foundry design reference manuals and resolve DRC issues at both block level and chip‑top integration level. Preferred: Experience with GAA (Gate‑All‑Around) technologies. Familiarity with digital standard‑cell layout design styles and methodologies. Experience with high‑performance, low‑power mixed‑signal or custom digital IP in advanced process nodes. Location: Austin, TX or San Diego, CA. Salary range: $116,500–$203,600 (depends on the location). Employee may be eligible for performance bonus, short‑ and long‑term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, company‑paid holidays, sick leave, vacation time, parental leave, 401(k) and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. #J-18808-Ljbffr