Senior Design Verification Engineer

Experience: 5 to 15 years of experience as a RTL Verification engineer.

Job Description:

System Verilog, UVM

Good knowledge in AMBA,AX4,AHB

IP/SS/SOC verification experience

Test Env, test case development

Regression debug, coverage analysis

Good knowledge in One of the High speed IF protocol like PCIe6, DDR5, Ethernet or USB3

Experience in Synopsys/Cadance Tools usage

Qualifications

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• Strong functional verification skills, including Functional Verification and Debugging for complex digital designs and SoCs.
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• Solid RTL Design expertise, with hands-on experience in writing, reviewing, and validating synthesizable RTL.
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• Proficiency in Formal Verification techniques and tools to complement simulation-based verification.
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• Good understanding of Computer Architecture concepts such as pipelines, caches, buses, and memory subsystems.
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• Experience with industry-standard verification languages and methodologies (e.g., SystemVerilog, UVM or similar frameworks).
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• Familiarity with simulation, coverage, and regression infrastructures and scripting (e.g., Python, Perl, or shell) to automate workflows.
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• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
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• Several years of relevant experience in ASIC/SoC verification, with a track record of successful tape-outs
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• Company Description Core ASIC Inc is a customer-focused VLSI design and verification services company with operations in Bangalore, India and Austin, Texas. The company delivers complete spec-to-silicon turnkey solutions, including firmware co-development, for custom semiconductor and IoT applications. Its silicon-proven platform solutions support IP design and verification, VIP development, SoC verification, and emulation services. Core ASIC emphasizes on-time delivery, close alignment with client vision, and a strong focus on time-to-market and ROI. A dedicated team of engineering, technology, and domain experts works as growth partners for clients across the product development lifecycle. or production silicon.
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• Ability to collaborate effectively in cross-functional teams, mentor junior engineers, and communicate clearly in written and verbal form.
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• Experience in IP verification, VIP development, or emulation/prototyping environments is a plus.
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